1. Technical Field
The present invention relates to a system and method for using resource pools and instruction pools for processor design verification and validation. More particularly, the present invention relates to a system and method for organizing processor resources into a resource pool, assigning the resource pool to a particular sub test case, and inserting instructions into the sub test case that utilize resources within the assigned resource pool.
2. Description of the Related Art
Processor testing tools exist whose goal is to generate the most stressful test case for a processor. In theory, the generated test case should provide maximum test coverage and should be interesting enough to stress various timing scenarios on the processor. The whole technology of these tools sits in the logic of building these test cases.
Verifying and validating a processor using test cases typically includes three stages, which are 1) test case build stage, 2) test case execution stage, and 3) validation and verification stage. A challenge found is that a large amount of test cases are usually generated in order to sufficiently test a processor. Unfortunately, this consumes a tremendous amount of upfront time, which leaves little time left to test the processor.
A test case shuffler process may be implemented that creates multiple test case scenarios from a single test case by shuffling the test case instruction order while maintaining relative sub test case instruction order. A challenge found, however, is that in order to implement the shuffler process, each sub test case's resource utilization should be mutually exclusive. Otherwise, if an instruction included in a sub test case is selected for insertion into the test case and the required resource is not dedicated to the sub test case, the instruction is aborted. In turn, the test case build time increases, which results in less time for processor verification and validation.
What is needed, therefore, is a system and method that that minimizes sub test case build times for use in a test case shuffler process.